MIC2225-4OYMT TR【PDF 11/15 页】IC REG DL BUCK/LINEAR 10TMLF

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Sheet目录44

7页 8页 9页 10页 [11页]12页 13页 14页 15页

Micrel, Inc.

MIC2225

February 2008

M9999-022008-D

Functional Description

VIN

VIN provides power to the MOSFETs for the switch

mode regulator section, along with the current limiting

sensing. Due to the high switching speeds, it is

recommended that an 1礔 capacitor be placed close to

VIN and the power ground (PGND) pin for bypassing.

Please refer to layout recommendations.

AVIN

Analog VIN (AVIN) provides power to the LDO section

and the bias through an internal 6& resistor. AVIN and

VIN must be tied together. Careful layout should be

considered to ensure high frequency switching noise

caused by VIN is reduced before reaching AVIN.

LDO

The LDO pin is the output of the linear regulator and

needs to be connected to a 2.2礔 output capacitor.

The enable pin provides a logic level control of the

output. In the off state, the supply current of the device is

greatly reduced (typically <1礎). Also, in the off state,

the output drive is placed in a "tri-stated" condition,

wherein both the high side P-channel MOSFET and the

low-side N-channel are in an off or non-conducting

state. Do not drive the enable pin above the supply

voltage.

ENLDO

The enable pin provides a logic level control of the LDO

output. In the off state, supply current of the device is

greatly reduced (typically <1礎). Do not drive the enable

pin above the supply voltage.

BIAS

The BIAS pin supplies the power to the internal power to

the control and reference circuitry. The bias is powered

from AVIN through an internal 6& resistor. A small 0.1礔

capacitor is recommended for bypassing.

The feedback pin (FB) provides the control path to

control the output. For fixed output, the controller

output is directly connected to the feedback (FB) pin.

The switch (SW) pin connects directly to the inductor

and provides the switching current necessary to operate

in PWM mode. Due to the high speed switching on this

pin, the switch node should be routed away from

sensitive nodes.

PGND

Power ground (PGND) is the ground path for the high

current PWM mode. The current loop for the power

ground should be as small as possible and separate

from the Analog ground (AGND) loop. Refer to the layout

considerations for more details.

SGND

Signal ground (SGND) is the ground path for the biasing

and control circuitry. The current loop for the signal

ground should be separate from the Power ground

(PGND) loop. Refer to the layout considerations for more

details.

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